1. Field of the Invention
This invention relates to a high speed synchronous counting system and to a process for increasing the speed capabilities of synchronous counters.
2. Description of Related Art
Until now, high speed synchronous counter configurations contained inherent delays which limited the speed at which the counters could operate. Some of these delays have been reduced through the use of a look-ahead carry signal which produces a carry signal one clock pulse before it is needed. However, even employing the one clock early look-ahead carries, the delay has only been reduced to a minimum of one gate delay. Typically, this translates to a guaranteed operating rate of 26 MHz using 70 MHz flip-flops.
High speed counters may be implemented by using gallium arsenide (GaAs) logic or high speed gate arrays. However, these are costly alternatives, compared to using slower, less expensive parts configured to provide increased speed performance.